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266 lines
7.9 KiB
266 lines
7.9 KiB
;**************************************************************** |
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; * |
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; Periph‚rique : DMA * |
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; Plages Entr‚es-Sorties : 0000-000F * |
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; 00C0-00DF * |
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; 0080-0090 * |
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; (0094-009F) * |
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; Plages M‚moires : AUCUNES * |
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; * |
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DmaRead equ 044h ;I/O to memory, no autoinit, increment, single mode |
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DmaWrite equ 048h ;Memory to I/O, no autoinit, increment, single mode |
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;Lecture des bits du registre d'‚tat (08, D0 ) |
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STATUS_REQ3 = 80h ;Bit actif: le canal DMA concern‚ |
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STATUS_REQ2 = 40h ;re‡oit une requˆte DMA |
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STATUS_REQ1 = 20h ;Request |
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STATUS_REQ0 = 10h |
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STATUS_TC3 = 08h ;Bit actif: Un transfert DMA a ‚t‚ |
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STATUS_TC2 = 04h ;ex‚cut‚ depuis la derniŠre lecture |
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STATUS_TC1 = 02h ;du registre d'‚tat. |
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STATUS_TC0 = 01h ;Terminal Count |
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;Ecriture des bits du registre de commande (08, D0) |
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COMMAND_DACKLEVEL = 80h ;Bit 7 actif: ligne DMA Acknowledge HIGH active |
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COMMAND_DREQLEVEL = 40h ;Bit 6 actif: ligne REQ Acknowledge LOW active |
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COMMAND_EXTWRITE = 20h ;Bit 5 actif: EXTENDED Write,sinon LATE Write |
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COMMAND_FIXEDPRI = 10h ;Bit 4 actif: priorit‚ constante |
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COMMAND_COMPRESS = 08h ;Bit 3 actif: compression |
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COMMAND_INACTIVE = 04h ;Bit 2 actif: contr“leur d‚sactiv‚ |
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COMMAND_ADH0 = 02h ;Bit 1 actif: Adress Hold pour canal 0/4 d‚sactiv‚ |
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COMMAND_MEM2MEM = 01h ;Bit 0 actif: m‚moire/m‚moire, sinon m‚moire/p‚riph‚rie |
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;Ecriture des bits du registre de requˆte ( 09, D2 ) |
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REQUEST_RESERVED = 0F8h ;R‚glage des bits r‚serv‚s =0 |
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REQUEST_SET = 04h ;D‚finir requˆte DMA |
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REQUEST_CLR = 00h ;Supprimer requˆte DMA |
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REQUEST_MSK = 03h ;Indiquer le canal dans les deux bits du bas |
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;Ecriture des bits du registre de masquage de canal ( 0A, D4 ) |
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CHANNEL_RESERVED = 0F8h ;R‚glage des bits r‚serv‚s =0 |
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CHANNEL_SET = 04h ;Masquer/verrouiller canal DMA |
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CHANNEL_CLR = 00h ;Lib‚rer canal DMA |
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CHANNEL_MSK = 03h ;Indiquer le canal dans les deux bits du bas |
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;Ecriture des bits du registre de mode (0B,D6) |
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MODE_DEMAND = 00h ;Transf‚rer … la demande |
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MODE_SINGLE = 40h ;Transf‚rer valeurs uniques |
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MODE_BLOCK = 80h ;Transf‚rer en bloc |
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MODE_CASCADE = 0C0h ;Transf‚rer en cascade |
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MODE_DECREMENT = 20h ;D‚cr‚menter |
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MODE_AUTOINIT = 10h ;Autoinitialisation vers la fin |
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MODE_VERIFY = 00h ;V‚rifier |
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MODE_WRITE = 04h ;Ecrire dans la m‚moire |
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MODE_READ = 08h ;Lire depuis la m‚moire |
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MODE_INVALID = 0Ch ;Incorrect |
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MODE_CHANNELMSK = 03h ;Indiquer le canal dans les deux bits du bas |
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;Ports du DMA esclave |
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DmaStatusS dw 08h ;R SLAVE Registre d'‚tat |
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DmaCommandS dw 08h ;W SLAVE Registre de commande |
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DmaRequestS dw 09h ;W SLAVE Ex‚cuter requˆte DMA |
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DmachMaskS dw 0ah ;W SLAVE Masquer canaux |
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DmaModeS dw 0bh ;W SLAVE Mode de transfert |
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DmaFlipFlopS dw 0ch ;W SLAVE Flipflop adr/compteur |
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DmaTempS dw 0dh ;R SLAVE Reset du contr“leur |
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DmaClearS dw 0dh ;R SLAVE Registre temporaire |
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DmaMaskClrS dw 0eh ;R SLAVE Lib‚rer canaux |
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DmaMaskS dw 0fh ;R SLAVE Masquer canaux |
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;Ports du DMA esclave |
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DmaStatusM dw 0D0h ;R MASTER Registre d'‚tat |
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DmaCommandM dw 0D0h ;W MASTER Registre de commande |
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DmaRequestM dw 0D2h ;W MASTER Ex‚cuter requˆte DMA |
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DmaMaskM dw 0D4h ;W MASTER Masquer canaux |
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DmaModeM dw 0D6h ;W MASTER Mode de transfert |
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DmaFlipFlopM dw 0D8h ;W MASTER Flipflop adr/compteur |
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DmaTempM dw 0DAh ;R MASTER Reset du contr“leur |
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DmaClearM dw 0DAh ;R MASTER Registre temporaire |
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DmaMaskClrM dw 0DCh ;R MASTER Lib‚rer canaux |
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DmaMaskM2 dw 0DEh ;R MASTER Masquer canaux |
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DmaAdress db 00h ;DMA address register 0 |
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db 002h ;DMA address register 1 |
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db 004h ;DMA address register 2 |
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db 006h ;DMA address register 3 |
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db 0c0h ;DMA address register 4 |
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db 0c4h ;DMA address register 5 |
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db 0c8h ;DMA address register 6 |
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db 0cch ;DMA address register 7 |
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DmaCount db 001h ;DMA count registers 0 |
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db 003h ;DMA count registers 1 |
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db 005h ;DMA count registers 2 |
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db 007h ;DMA count registers 3 |
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db 0c2h ;DMA count registers 4 |
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db 0c6h ;DMA count registers 5 |
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db 0cah ;DMA count registers 6 |
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db 0ceh ;DMA count registers 7 |
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DmaPage db 087h ;DMA page registers 0 |
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db 083h ;DMA page registers 1 |
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db 081h ;DMA page registers 2 |
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db 082h ;DMA page registers 3 |
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db 08fh ;DMA page registers 4 |
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db 08bh ;DMA page registers 5 |
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db 089h ;DMA page registers 6 |
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db 08ah ;DMA page registers 7 |
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;verouille le canal AL |
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DisableDma: |
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push ax dx |
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cmp al, 4 |
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jae MasterDisableDma |
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mov dx, DmaMaskS |
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or al, 00000100b |
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out dx, al |
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jmp EndDisableDma |
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MasterDisableDma: |
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mov dx, DmaMaskS |
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and al, 00000011b |
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or al, 00000100b |
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out dx, al |
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EndDisableDma: |
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pop dx ax |
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ret |
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;déverouille le canal AL |
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EnableDma: |
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push ax dx |
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cmp al, 4 |
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jae MasterDisableDma |
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mov dx, DmaMaskS |
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out dx, al |
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jmp EndEnableDma |
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MasterEnableDma: |
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mov dx, DmaMaskS |
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and al, 00000011b |
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out dx, al |
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EndEnableDma: |
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pop dx ax |
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ret |
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;Efface le FlipFlop canal AL |
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ClrDmaFlipFlop: |
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push ax dx |
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cmp al, 4 |
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jae MasterClrFlipFlopDma |
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mov dx,DmaFlipFlopS |
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xor ax, ax |
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out dx, al |
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jmp EndClrFlipFlopDma |
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MasterClrFlipFlopDma: |
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mov dx,DmaFlipFlopM |
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xor ax, ax |
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out dx, al |
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EndClrFlipFlopDma: |
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pop dx ax |
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ret |
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;Met le mode du canal al à ah |
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SetDmaMode: |
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push ax dx |
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cmp al, 4 |
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jae MasterSetDmaMode |
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mov dx,DmaModeS |
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or al, ah |
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out dx, al |
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jmp EndSetDmaMode |
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MasterSetDmaMode: |
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mov dx,DmaModeM |
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and al, 00000011b |
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or al, ah |
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out dx, al |
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EndSetDmaMode: |
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pop dx ax |
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ret |
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;Met le page du canal al a ah |
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SetDmaPage: |
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push ax bx dx si |
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cmp al, 4 |
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jae MasterSetDmaPage |
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mov si, offset DmaPage |
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xor dh, dh |
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xor bh, bh |
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mov bl, al |
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mov dl, cs:[si+bx] |
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xchg al, ah |
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out dx, al |
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jmp EndSetDmaPage |
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MasterSetDmaPage: |
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EndSetDmaPage: |
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pop si dx bx ax |
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ret |
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;Met l'adresse du canal al a DS:BX |
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SetDmaAdress: |
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push ax bx cx dx si |
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push ax |
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mov ax, ds |
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and ax, 0000111111111111b |
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shl ax,4 |
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add bx, ax |
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mov ax, ds |
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and ax, 1111000000000000b |
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shr ax, 4 |
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mov cx,ax |
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pop ax |
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push ax |
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add ax,cx |
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call SetDmaPage |
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pop ax |
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call ClrDmaFlipFlop |
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mov si, offset DmaAdress |
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xor dh, dh |
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push bx |
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xor bh, bh |
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mov bl, al |
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mov dl, byte ptr cs:[si+bx] |
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pop bx |
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cmp al, 4 |
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jae MasterSetDmaAddress |
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mov al, bh |
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out dx, al |
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mov al, bl |
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out dx, al |
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jmp EndSetDmaAddress |
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MasterSetDmaAddress: |
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mov al, bh |
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out dx, al |
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call ClrDmaFlipFlop |
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mov al, bl |
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out dx, al |
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EndSetDmaAddress: |
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pop si dx cx bx ax |
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ret |
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;Spécifie au controleur DMA le nombre d'octets à transférer dans CX |
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SetDmaCount: |
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push ax bx dx si |
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call ClrDmaFlipFlop |
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mov si, offset DmaCount |
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xor dh, dh |
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xor bh, bh |
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mov bl, al |
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mov dl, byte ptr cs:[si+bx] |
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cmp al, 4 |
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jae MasterSetDmaCount |
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mov al, ch |
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out dx, al |
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mov al, cl |
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out dx, al |
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jmp EndSetDmaCount |
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MasterSetDmaCount: |
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mov al, ch |
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out dx, al |
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call ClrDmaFlipFlop |
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mov al, cl |
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out dx, al |
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EndSetDmaCount: |
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pop si dx bx ax |
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ret |
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